Fast, automated generation of high performance simulators for microprocessors
An Austrian company has developed a platform for virtual exploration, simulation, and verification of microprocessor architectures. Via a generator tool, a microprocessor architecture description can be automatically transformed into a simulator software tool for the respective microprocessor architecture within minutes with outstanding performance. So the duration and costs of the whole simulation process can be extremely reduced. The company is looking for technical cooperation agreements.
Type of partner sought: companies Role of partners sought: They are looking for pilot customers requiring an easily re-targetable simulator tool for their microprocessor- architecture or microprocessor-technology developments. They will work with pilot customers by providing guidance, development support, and training to generate a microprocessor simulation for their specific architecture.
The Austrian company is a service and technlogy provider in the embedded systems and IoT market. When designing a new or modifying an existing microprocessor architecture it is expedient to evaluate the architecture as early as possible in the design process in order to avoid costly redesign cycles. This might ideally happen in a state when the microprocessor hardware is not yet available. One way to perform early design evaluation is the usage of simulator software which mimics the characteristics of the microprocessor architecture and does not require the microprocessor hardware to be available. Yet the development of simulator software requires manual development and cannot be achieved with little effort. Using the simulator platform, a microprocessor's architecture description, which is usually available to fabricate the actual microprocessor hardware, is automatically converted into source code for a simulator tool efficiently and in short time. The simulator platform includes dedicated components to facilitate this generation process. An input converter that understands several established architecture description formats reads in a particular description and converts it to an internal architecture representation. A generator tool creates source code for a simulator tool from this internal architecture representation. Moreover, pre-built modules include a pallet of performance features which can be integrated into every generated simulator. In case an architecture description format is not known to the input converter module it can be easily adapted. Once the generated simulator source code and the pre-built modules are combined and built into a simulator tool, evaluation can start and programs intended for the respective microprocessor architecture can be loaded and executed in the simulator tool to examine the architecture's capabilities and performance. The simulator platform is currently aimed at RISC, DSP, and IoT microprocessors families. However, other architecture types like AI microprocessors can potentially be supported. A simulator tool for the RISC-V instruction set architecture is available. RISC-V is an open microprocessor architecture which can be freely adapted and enhanced by microprocessor hardware or IP manufacturers making the simulator platform an ideal environment for such developments. The simulator platform is available for Linux and Windows host platforms. They are looking for technical cooperation agreements. The pilot customers shall require an easily re-targetable simulator tool for their microprocessor- architecture or microprocessor-technology developments. They will work with pilot customers by providing guidance, development support, and training to generate a microprocessor simulation for their specific architecture.
Advantages and innovations
The simulator platform consists of a framework with state of the art simulation features and of a generator tool, that supports the user to quickly create a simulator tool customized for a specific microprocessor architecture. Microprocessor architecture changes or enhancements, like the modification of the instruction set or the register set, can be easily modeled into a simulation tool enabling early architecture evaluation. By reducing simulator tool development and verification time microprocessor architecture evaluation cycles can be shortened and/or the number of evaluation cycles can be increased without impacting development schedules. The simulation concept allows for outstanding simulation speed up to 10 times (i.e. 400 to 1000 MIPS) as fast as conventional simulators, while providing instruction execution accuracy and cycle approximation. This flexible simulator platform is based on a modular concept which can be easily enhanced according to user requirements.
Available for demonstration
Intellectual Property Rights (IPR)
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